tm december 2008 ?2008 fairchild semiconductor corporation FDMA3023PZ rev . b1 www.fairchildsemi.com 1 FDMA3023PZ dual p-channel powertrench ? mosfet FDMA3023PZ dual p-channel powertrench ? mosfet -30 v, -2.9 a, 90 m ? features ? max r ds(on) = 90 m ? at v gs = -4.5 v, i d = -2.9 a ? max r ds(on) = 130 m ? at v gs = -2.5 v, i d = -2.6 a ? max r ds(on) = 170 m ? at v gs = -1.8 v, i d = -1.7 a ? max r ds(on) = 240 m ? at v gs = -1.5 v, i d = -1.0 a ? low profile - 0.8 mm maximum - in the new package microfet 2x2 mm ? hbm esd protection level > 2 kv (note 3) ? rohs compliant ? free from halogenated compounds and antimony oxides general description this device is designed specifically as a single package solution for the battery charge switch in cellular handset and other ultra-portable applications. it features two independent p-channel mosfets with low on- state resistance for minimum conduction losses. when connec ted in the typical common source configuration, bi-directi onal current flow is possible. the microfet 2x2 package offers exceptional thermal performance for its physical size and is well suited to linear mode applications. 3 2 1 4 5 6 3 2 1 4 5 6 3 2 1 4 5 6 3 2 1 4 5 6 3 2 1 4 5 6 3 2 1 4 5 6 g2 s1 g1 d2 d1 s2 s1 g1 d2 s2 microfet 2x2 d1 g2 pin 1 d1 d2 6 5 4 1 2 3 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage -30 v v gs gate to source voltage 8 v i d drain current -continuous (note 1a) -2.9 a -pulsed -6 p d power dissipation (note 1a) 1.4 w power dissipation (note 1b) 0.7 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance for single oper ation, junction to ambient (note 1a) 86 c/w r ja thermal resistance for single oper ation, junction to ambient (note 1b) 173 r ja thermal resistance for dual operation, j unction to ambient (note 1c) 69 r ja thermal resistance for dual operation, junction to ambient (note 1d) 151 device marking device package reel size tape width quantity 323 FDMA3023PZ microfet 2x2 7 ?? 8 mm 3000 units
www.fairchildsemi.com 2 ?2008 fairchild semiconductor corporation FDMA3023PZ rev . b1 FDMA3023PZ dual p-channel powertrench ? mosfet electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = -250 a, v gs = 0 v -30 v ? bv dss ? t j breakdown voltage temperature coefficient i d = -250 a, referenced to 25 c -24 mv / c i dss zero gate voltage drain current v ds = -24 v, v gs = 0 v -1 a i gss gate to source leakage current v gs = 8 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = -250 a -0.4 -0.6 -1.0 v ? v gs(th) ? t j gate to source threshold voltage temperature coefficient i d = -250 a, referenced to 25 c 3 mv/c r ds(on) static drain to source on resistance v gs = -4.5 v, i d = -2.9 a 71 90 m ? v gs = -2.5 v, i d = -2.6 a 97 130 v gs = -1.8 v, i d = -1.7 a 122 170 v gs = -1.5 v, i d = -1.0 a 151 240 v gs = -4.5 v, i d = -2.9 a, t j = 125 c 110 140 g fs forward transconductance v ds = -5 v, i d = -2.9 a 10 s c iss input capacitance v ds = -15 v, v gs = 0 v, f = 1 mhz 400 530 pf c oss output capacitance 55 70 pf c rss reverse transfer capacitance 45 65 pf t d(on) turn-on delay time v dd = -15 v, i d = -1.0 a, v gs = -4.5 v, r gen = 6 ? 510ns t r rise time 410ns t d(off) turn-off delay time 62 100 ns t f fall time 18 33 ns q g(tot) total gate charge v dd = -15 v, i d = -2.9 a v gs = -4.5 v 7.9 11 nc q gs gate to source charge 0.9 nc q gd gate to drain ?miller? charge 1.9 nc i s maximum continuous drain-source diode forward current -1.1 a v sd source to drain diode forward voltage v gs = 0 v, i s = -1.1 a (note 2) -0.8 -1.2 v t rr reverse recovery time i f = -2.9 a, di/dt = 100 a/ s 18 33 ns q rr reverse recovery charge 6.6 13 nc
www.fairchildsemi.com 3 ?2008 fairchild semiconductor corporation FDMA3023PZ rev . b1 FDMA3023PZ dual p-channel powertrench ? mosfet notes: 1. r ja is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ja is determined by the user's board design. (a) r ja = 86 c/w when mounted on a 1 in 2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick pcb. for single operation. (b) r ja = 173 c/w when mounted on a minimum pad of 2 oz copper. for single operation. (c) r ja = 69 o c/w when mounted on a 1 in 2 pad of 2 oz copper, 1.5 ? x 1.5 ? x 0.062 ? thick pcb. for dual operation. (d) r ja = 151 o c/w when mounted on a minimum pad of 2 oz copper. for dual operation. 2. pulse test : pulse width < 300 us, duty cycle < 2.0% 3. the diode connected between the gate and source serves only as protection against esd. no gate overvoltage rating is implied . a)86 o c/w when mounted on a 1 in 2 pad of 2 oz copper. b)173 o c/w when mounted on a minimum pad of 2 oz copper. c)69 o c/w when mounted on a 1 in 2 pad of 2 oz copper. d)151 o c/w when mounted on a minimum pad of 2 oz copper.
www.fairchildsemi.com 4 ?2008 fairchild semiconductor corporation FDMA3023PZ rev b1 FDMA3023PZ dual p-channel powertrench ? mosfet typical characteristics t j = 25 c unless otherwise noted figure 1. 0 0.5 1.0 1.5 2.0 0 1 2 3 4 5 6 v gs = -2.5 v v gs = -4.5 v v gs = -3.5 v pulse duration = 80 p s duty cycle = 0.5% max v gs = -1.8 v v gs = -1.5 v -i d , drain current (a) -v ds , drain to source voltage (v) on region characteristics figure 2. 123456 0 1 2 3 4 5 6 v gs = -3.5 v v gs = -1.8 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance -i d , drain current (a) v gs = -4.5 v v gs = -2.5 v v gs = -1.5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = -2.9 a v gs = -4.5 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 100 200 300 400 i d = -1.45 a t j = 25 o c t j = 125 o c -v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 0.5 1.0 1.5 2.0 0 1 2 3 4 5 6 v ds = -5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c t j = 125 o c -i d , drain current (a) -v gs , gate to source voltage (v) figure 6. 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0 v -i s , reverse drain current (a) -v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
www.fairchildsemi.com 5 ?2008 fairchild semiconductor corporation FDMA3023PZ rev b1 FDMA3023PZ dual p-channel powertrench ? mosfet figure 7. 0246810 0 1 2 3 4 5 q g , gate charge (nc) -v gs , gate to source voltage (v) i d = -2.9 a v dd = -15 v v dd = -20 v v dd = -10 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) -v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 03691215 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 v gs = 0 v t j = 25 o c t j = 125 o c -v gs , gate to source voltage (v) -i g , gate leakage current (a) gate leakage vs gate to source voltage figure 10. 0.01 0.1 1 10 100 0.01 0.1 1 10 10 ms dc 10 s 1 s 100 ms 1 ms -i d , drain current (a) -v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 173 o c/w t a = 25 o c 200 forward bias safe operating area figure 11. single pulse maximum power dissipation 10 -3 10 -2 10 -1 110 1000 0.5 1 10 100 200 p ( pk ) , peak transient power (w) t, pulse width (sec) v gs = -4.5 v single pulse r t ja = 173 o c/w t a = 25 o c typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 6 ?2008 fairchild semiconductor corporation FDMA3023PZ rev b1 FDMA3023PZ dual p-channel powertrench ? mosfet figure 12. 10 -3 10 -2 10 -1 110 100 1000 0.005 0.01 0.1 1 2 single pulse r t ja = 173 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 7 ?2008 fairchild semiconductor corporation FDMA3023PZ rev . b1 FDMA3023PZ dual p-channel powertrench ? mosfet dimensional outlin e and pad layout b. dimensions are in millimeters. c. di mensi ons and tolerances per mlp06jrevb a. conforms to jedec regi strati on mo-229, variation vccc except as noted. asme y14.5m, 1994 top view bottom view recommended land pattern b a c 2x 2x side view 0.20 pin#1 ident 0.25~0.35 (1.80) (0.10) 0.65 (0.42) (0.42) (1.00) (0.50) (2.25) (0.80) (0.20) 0.8 max 0.05 0.00 2.0 2.0 1.64? .10 1.30 0.65 0.86? .10 (0.65) 0.35 0.35? .10 pi n#1 quadrant (0.185) d. non-jedec dual dap d
FDMA3023PZ dual p-channel powertrench ? mosfet ?2008 fairchild semiconductor corporation 8 www.fairchildsemi.com FDMA3023PZ rev . b1 rev. i37 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. * ezswitch? and flashwriter ? are trademarks of system general corporati on, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fai rchild semiconductor corporation. as used herein: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform c an be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. build it now? 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